As input/output speeds of memory devices have increased in recent years, newer implementations have begun to approach performance limitations, thereby exhausting the utility of conventional architectures.
Consequently, to compensate, some approaches have turned toward adopting multi-channel memory architectures, wherein a memory unit may be accessed by simultaneous commands via separate, independent logical channels. This allows commands to pass through command queues at a more efficient rate as commands may be provided as soon as a channel becomes available. In short, the amount of time a command is held in a queue is reduced.
However, this approach is not without its drawbacks. Traditionally, the ordering of commands by a memory controller have been enforced at the transaction queue level. That is, ordering logic has been used to enforce particular ordering rules on the command queue for providing commands to the memory units such that the order in which responses are returned from memory units is in accordance with a desired response order. Therefore, under this scheme, the performance of a multi-channel memory access scheme is hindered by the fact that some commands cannot be provided (e.g. issued) even when a channel is available as, in some cases, a response corresponding to a prior command must be received from a memory unit before the waiting command can be provided. While this implementation ensures that responses are returned in the correct order, available channels remain unused while the memory controller waits to receive the response from the memory unit.
Accordingly, there is therefore a need for an improved memory apparatus and method that utilizes multi-channel memory accesses and provides commands to memory units over available channels irrespective of when responses are provided.